A conventional variable delay line DL typically comprises an inductance element L consisting of a solenoid and provided with a plurality of taps as shown in FIG. 14. These taps are connected to the cathodes of variable capacitance diodes Dv whose anodes are grounded by way of a bypass capacitor Cp. The output end of the delay line DL is connected to a terminal resistor RL. An analog control voltage Vd (reverse voltage) generated by a D/A converter DAC having input terminals D.sub.0 through D.sub.n-1 for an n-bit digital signal is supplied to the anodes of the variable capacitance diodes Dv. The D/A converter DAC produces an analog control signal according to the bit structure of the signal provided to its input terminals.
The input end and the output end of the delay line DL are typically connected to an input terminal 1 and an output terminal 3 by way of respective buffer circuits which may consist of inverters I.
In this variable delay line DL, as the bit structure of the digital control signal is varied, the analog control signal accordingly changes and so does the delay time of the delay line DL. Thus, a variable delay line of this type can be used as a programmable delay line.
This delay line has the advantage that the structure is simple and the delay time can be electronically varied in very small steps, but has some shortcomings as described in the following.
The graph in FIG. 15 shows the change in the characteristic impedance Z.sub.0 and the delay time t.sub.d of the delay line DL in relation with the control voltage Vd. It can be seen that the characteristic impedance Z.sub.0 and the delay time t.sub.d of the delay line DL change in opposite directions and in nonlinear fashion as the control voltage Vd is varied. Therefore, impedance matching between the delay line DL and the terminal resistor RL is possible only at one point in the whole variable range of the variable delay line DL and the state of impedance mismatching is therefore present in most of the variable range of the variable delay line DL. Therefore, an input signal produces reflected waves in the variable delay line in most part of the variable range of the variable delay line DL. Particularly when a high speed signal is supplied to the variable delay line DL, the reflected waves tend to distort the output signal.